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Order Number: MC33883/D Rev 3.2, 05/2001
MC33883
Advance Information
55 VOLTS
SEMICONDUCTOR TECHNICAL DATA
Full Bridge Pre-Driver
The MC33883 is a full bridge pre-driver including integrated charge pump, two independent high and low side driver channels. The drive outputs are capable to source and sink 1 A pulse peak current. The low side channel is referenced to ground, the high side channel is floating above ground. A linear regulator provides a maximum of 16.5V to supply the low side gate driver stages. The high side driver stages are supplied with a 10Vtypical charge pump voltage. Such built-in feature, associated to external capacitor provides a full floating high side drive. An under- and over-voltage protection prevents erratic system operation at abnormal supply voltages. Under fault, these functions force the driver stages into off state. The logic inputs are compatible with standard CMOS or LSTTL outputs. The input hysteresis makes the output switching time independent of the input transition time. The global enable logic signal can be used to disable the charge pump and all the bias circuit. The net advantage is the reduction of the quiescent supply current to under 10A. To wake up the circuit, 5 V has to be provided at G_EN. * VCC Operating Voltage Range from 5.5 V up to 55 V * VCC2 Operating Voltage Range from 5.5 V up to 28 V * Automotive Temperature Range -40C to 125C * 1A Pulse Current Output Driver * Fast PWM Capability * Built-In Charge Pump
VCC C2 CP_OUT SRC_HS1 GATE_HS1 IN_HS1 IN_LS1 GATE_LS1 GND1
DW SUFFIX PLASTIC PACKAGE CASE 751D-05
PIN CONNECTIONS (TOP VIEW) CASE 751D-05
1 2 3 4 5 6 7 8 9
20 19 18 17 16
G_EN SRC_HS2 GATE_HS2 IN_HS2 IN_LS2
1 5 GATE_LS2 14 13
GND2 C1
1 2 GND_A 11
LR_OUT 10
VCC2
ORDERING INFORMATION
Device PC33883DW
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc., 2001. All rights reserved. Page 1 of 11
Temperature Range -40oC to +125oC
Package
SOIC20
DEVICE DESCRIPTION Figure 1: Principal Building Blocks
Ccp C1 VCC UV/OV Detect VDD VCC VCC RDY EN GND G_EN VCC2 VCC2 EN +14.5 V VDD Charge Pump C1 C2 Vpos +14.5 V Vgs_hs Vgs_ls VCC VCC CCP_OUT5.5 V... 55 V CP_OUT CLR_OUT LR_OUT C2 VCC2 VCC2 5.5 V... 28 V
Linear +5.0 V Reg GND +14.5 V HIGH AND LOW SIDE CONTROL WITH CHARGE PUMP
BRG_EN
VCC Vgs_hs VDD/VPOS Level Shift Input & CCS Pulse Generator G_LOW_H G_LOW_LS IN Output OUT GATE_HS1 SRC_HS1
IN_HS1
IN_LS1 LOGIC VDD/VCC Level Shift Pulse Generator
Vgs_Is
IN Output OUT GATE_LS1
HIGH AND LOW SIDE CHANNEL WITH CROSS CONDUCTION SUPPRESSION
BRG_EN
CCS VCC Vgs_hs
IN_HS2
VDD/VPOS Level Shift
Pulse Generator G_LOW_H G_LOW_LS
IN Output
OUT
GATE_HS2 SRC_HS2
IN_LS2
Input & CCS VDD/VCC Level Shift
Vgs_Is
IN Output OUT GATE_LS2
Pulse Generator
GND
MC33883
Page 2 of 11
ABSOLUTE MAXIMUM RATINGS: Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND
Rating Supply Voltage1 Supply Voltage2 (NOTE 1) Linear Regulator Output Voltage High Side Floating Supply Absolute Voltage High Side Floating Source Voltage High Side Source Current from Cpout in Switch On State High Side Gate Voltage High Side Gate Source Voltage
Symbol VCC VCC2 VLR_out VCP_OUT VSRC_HS IS VGATE_HS VGATE_HS - VSRC_HS VCP_OUT - VGATE_HS VGATE_LS VG_EN VIN VC1 VC2 VESD VESD2
Min -0.3 -0.3 -0.3 -0.3 -0.3
Max 65 35 18 65 65 250
Unit V V V V V mA V V
-0.3 -0.3
65 20
High Side Floating Supply Gate Voltage
-0.3
65
V
Low Side Output Voltage Wake up Voltage Logic Input Voltage Charge Pump Capacitor Voltage Charge Pump Capacitor Voltage ESD Voltage on all Pins except the case of (Pin C2 respect to PinVcc) (HBM, 100pF, 1.5kOhms) ESD Voltage (PinC2 respect to Pin Vcc) Power Dissipation and Thermal Characteristics Maximum Power Dissipation@25C Thermal Resistance Junction-to-Air Operating Junction Temperature Storage Temperature OPERATING CONDITIONS:
Typical values for TA = 25C, Min/Max values for TA = -40C to +125C Rating
-0.3 -0.3 -0.3 -0.3 -0.3 -2.0
17 35 10 VLR_OUT 65 2.0
V V V V V KV
-1.7
1.7
KV
PD RJA TJ Tstg -40 -65
1.25 100 +150 +150
W C/W C C
Symbol
Min
Max
Unit
Supply Voltage1 Supply Voltage2 High Side Floating Supply Absolute Voltage
VCC VCC2 VCP_OUT
5.5 5.5 VCC+4
55 28 VCC+11but<65
V V V
NOTE1: VCC can sustain load dump pulse 40V, 400ms, 2Ohms
MC33883
Page 3 of 11
STATIC ELECTRICAL CHARACTERISTICS VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise specified. Typical values for TA = 25C, Min/Max values for TA = -40C to +125C, unless otherwise specified.
Characteristics LOGIC SECTION Logic "1" Input Voltage (IN_LS & IN_HS) Logic "0" Input Voltage (IN_LS & IN_HS) Logic "1" Input Current Vin=5V Logic "0" Input Current Vin=0V Wake Up Input Voltage (G_EN) Wake Up Current (G_EN) VG_EN = 14 V Wake Up Current (G_EN) VG_EN = 28V LINEAR REGULATOR SECTION Linear Regulator VLR_OUT @ VCC2 from 15.0 to 28 V, ILOAD from 0mA to 20mA Linear Regulator VLR_OUT @ ILOAD = 20mA VLR_OUT @ILOAD =20mA, VCC2 =5.5V, VCC = 5.5V CHARGE PUMP SECTION Charge Pump Output Voltage, referenced to VCC VCC=12V ILOAD = 0mA, CCpout=1uF Charge Pump Output Voltage, referenced to VCC VCC=12V ILOAD = 7mA, CCpout=1uF Charge Pump Output Voltage, referenced to VCC VCC2 = VCC=5.5V ILOAD = 0mA, CCpout=1uF Charge Pump Output Voltage, referenced to VCC VCC2 = VCC=5.5V ILOAD = 7mA, CCpout=1uF Charge Pump Output Voltage, referenced to VCC VCC=55V ILOAD = 0mA, CCpout=1uF Charge Pump Output Voltage, referenced to VCC VCC=55V ILOAD = 7mA, CCpout=1uF Peak current through pin C1 under rapid changing Vcc voltages (see Figure 5) Minimum peak voltage at pinC1 under rapid changing Vcc voltages (see Figure 5)
Pin #
Symbol
Min
Typ
Max
Unit
6, 7, 16, 17
VIH VIL
2.0
10 0.8
V V uA uA V uA mA
6, 7, 16, 17
Iin+ Iin-
200 200 4.5 5.0 200
1000 1000 VCC2 500 1.5
27 27 27
VG_EN IG_EN IG_EN2
10
VLR_OUT VLR_OUT
12.5
16.5
V
10 10
VCC2 1.5 4.0
V
V
3
VCP_OUT
7.5
V
3
VCP_OUT
7.0
V
3
VCP_OUT
2.3
V
3
VCP_OUT
1.8
V
3
VCP_OUT
7.5
V
3
VCP_OUT
7.0
V
13 13
IC1 VC1min
-2.0 -1.5
2.0
A V
MC33883
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Characteristics SUPPLY VOLTAGE SECTION Quiescent Vcc Supply Current VG_EN=0V @Vcc=12V Quiescent Vcc Supply Current VG_EN=0V @Vcc=55V Operating Vcc Supply Current (@VCC=55V and VCC2=28V) (@VCC=12V and VCC2=12V) Logic imput pin inactive (high impedance) Additional Operating Vcc Supply Current for EACH logic input pin active @VCC=55V and VCC2=28V. (Note1) Quiescent Vcc2 Supply Current VG_EN=0V @ Vcc2 = 12V Quiescent Vcc2 Supply Current VG_EN=0V @ Vcc2 = 28V Operating Vcc2 Supply Current (@VCC=55V and VCC2=28V) (@VCC=12V and VCC2=12V) Logic input pin inactive (high impedance) Additional Operating Vcc2 Supply Current for EACH logic input pin active @VCC=55V and VCC2=28V. (Note1) Under Voltage Shutdown VCC2 (Note2) Under Voltage Shutdown VCC Over Voltage Shutdown VCC Over Voltage Shutdown VCC2 OUTPUT SECTION Output Sink Resistance (Turned off) VGATE_HS - VSRC_HS =1V Output Source Resistance (Turned on) VCP_OUT - VGATE_HS =0.1V High Side Source Current from CPOUT in Switch On State Max Voltage (VGATE_HS - VSRC_HS), INH=1, ISmax=5mA
Pin #
Symbol
Min
Typ
Max
Unit
1
10
uA
1
10
uA
1 1
2.2 0.7
mA mA
1
5
mA
11
5
uA
11
5
uA
11 11
10 9
mA mA
11
5
mA
11 1 1 11
UV2 UV OV OV2
4.0 4.0 57 29.5
5.0 5.0 61 31
5.5 5.5 65 35
V V V V
RDS 3, 4, 5, 8, 15, 18, 19 RDS 4, 19 ISmax
22.0
Ohms
22.0
Ohms
200 18
mA V
4, 5, 18, 19
Note 1:Large duty cycles of the logic inputs will result in a large power dissipation within the device, that possibly could surpass the package power handling rating. Note2: Between 4.0V and 5.5V, the device can exhibt a non erroneous behaviour.
MC33883
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DYNAMIC ELECTRICAL CHARACTERISTICS: VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise specified. Typical values for TA = 25C, Min/Max values for TA = -40C to +125C, unless otherwise specified
Characteristics Prop. Delay HS and LS, Cload=5nF; Between 50% Input to 50% Output ( see Figure 2:) Turn On Rise Time, Cload=5nF ; 10% to 90% (NOTE 3) ( see Figure 2:) Turn Off Fall Time, Cload=5nF ; 10% to 90% (NOTE 3) (seeFigure 2:)
Pin # 5, 6, 7, 8, 15, 16, 17, 18
Symbol tPD
Min
Typ 200
Max 300
Unit ns
tr tf 5, 8, 15, 18
80 80
180 180
ns ns
NOTE 1: Characterization only NOTE 2: Input overdrive 1V NOTE 3: Rise time is given by time needed to charge the gate from 1V to 10V (Vice versa for fall time) NOTE : Cload corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side.
Figure 2: Dynamic Characteristics
/IN_HS or /IN_LS 50% 50%
50% IN_HS or IN_LS GATE_HS or GATE_LS
tpd tpd
50%
50%
tf tr
50% 10% 90% 90% 10%
MC33883
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DEVICE DESCRIPTION
Driver Characteristics Turn-On: For turn-on the current required to charge the gate source capacitor Ciss in the specified time can be calculated as follows: Peak Current for Rise/Fall Time (tr) and a typical PowerMosFET Gate Charge Qg IP = Qg/tr = 80nC/80 ns 1.0 A Turn-Off: The peak current for turn-off can be obtained in the same way as for turn-on. In addition to the dynamically current, required to turn-off or turn-on the FET, various application related switching scenarios have to be considered: The output driver sources a peak current of up to 1A for 200ns to turn on the gate. After 200ns, 100mA is provided continuously to maintain the gate charged. The output driver sinks a peak current of up to 1A for 200ns to turn off the gate. After 200ns, 100mA are sinked continuously to maintain the gate discharged. In order to withstand high dV/dt spikes a low resistive path between gate and source is implemented during the off state.
Figure 3:
Flyback Spike charge LSGate via Crss Charge Current Irss up to 2.0 A! Uncontrolled Turn-On of Low Side FET
Flyback Spike pull down HS-Drain VGS Increase Delayed Turn-Off of High Side FET
Flyback Spike charge LS-Gate via Crss Charge Current Irss up to 2.0 A! Delayed TurnOff of Low Side FET
Flyback Spike pull down HS-Drain VGS Increase Uncontrolled Turn-On of High Side FET
Crss
VBAT
Crss
VBAT OFF
Crss
VBAT OFF VGATE -VDRN L1 ILOAD g_hs
Crss
VBAT
g_hs
g_hs ILOAD Ciss Crss ILOAD
g_hs
Ciss Irss VGATE g_ls OFF Ciss Crss
L1
L1
Ciss Crss
Ciss Crss
L1
ILOAD
g_ls OFF Ciss
g_ls
g_ls
Ciss
Ciss
Driver Requirement: Low Resistive Gate-Source Path during OFF-State
Driver Requirement: Low Resistive Gate Source Path during OFFState. High Peak Sink Current Capab.
Driver Requirement: High Peak Sink Current Capab.
Driver Requirement: Low Resistive Gate-Source Path during OFF-State
MC33883
Page 7 of 11
DEVICE DESCRIPTION
Driver Supply The High Side(HS) Driver is supplied from the internal charge pump buffered at CP_OUT. The low-drop regulator provides approx. 4mA (fPWM = 50KHz) per HS gate. In case of the full bridge that means approximately 16mA, 8.0 mA for the high side and 8.0 mA for the low side. (Note: The average current required to switch a gate with a frequency of 100KHz is: Average Current (Charge Pump) for PWM Frq. (fPWM) ICP = Qg*fPWM = 80nC*100 kHz = 8.0mA A full bridge application switch only one high side and one low side at the same time.) External capacitors on Charge Pump and on Linear Regulator are necessary to supply high peak current absorbed during switching. The Low Side Driver is supplied from built in low drop regulator. Gate Protection The low side gate is protected by the internal linear regulator, which guarantees that VGATE_LS does not exceed the maximum VGS. Especially when working with the charge pump the voltage at POS_HS can be up to 65V. The high side gate is clamped internally, in order to avoid a VGS exceeding 18V. The Gate protection does not include a Flyback Voltage Clamp that protects the driver and the external FET from a Flyback voltage that can appear when driving inductive load.This Flyback voltage can reach high negative voltage values and needs to be clamped externally. (Gate = VCC, or Gate = Gnd) the function of the remaining output driver stages is not affected. All output drivers are short circuit protected against short circuits to ground. Logic Inputs Logic Input Voltage Range: Absolute Max : -0.3V ... 10V Wake Up Function: (G_EN) 4.5V ... VCC2 During Wake-Up the logic is supplied from the G_EN pin. Low Drop Linear Regulator The low drop linear regulator provides the 5.0V for the logic section of the driver, the Vgs_ls buffered at LR_OUT and the +14.5V for the charge pump, which generates the Vgs_hs. The low drop linear regulator provides 4.0mA average current per driver stage. If typically VCC2 exceeds 15.0V the output is limited to 14.5Vtyp. Charge Pump The charge pump generates the high side driver supply voltage (VGS_HS), buffered at CP_OUT. Vgs_hs = VCC + VLR_OUT - 2V. The average output current is ICP = 4.0 mA (fPWM = 50 KHz) per output driver. The charge pump charges an external storage capacitor, which provides the peak switching current to the high side output drivers. N.B. In some applications a large dV/dt at Pin C2 due to sudden changes at VCC can cause a large peak currents flowing through Pin C1. Positive transitions at Pin C2 ;mimimum peak current : Ic1min = 2.0A tc1min = 600ns (see Figure 5:for peak description) Negative transitions at Pin C2; maximum peak current : Ic1max = 2.0A tc1max = 600ns (see Figure 5 for peak description) Current sourced by Pin C1 during a large dV/dt will result in a negative voltage at Pin 13; negative transitions at Pin C2; minimum peak voltage: Vc1min = -1.5V tc1max = 600ns (see Figure 5:for peak description)
Figure 4: Gate Protection & Flyback Voltage Clamp
Vgs_ls Vgs_hs M1 IN OUT Output Driver GATE_HS VGS < 14 V SRC_HS Dcl G_LOW IN OUT Output Driver GATE_LS M2 L1 under all conditions Inductive Flyback Voltage Clamp VCC
G_LOW
TMOS Failure Protection All output driver stages are protected against TMOS failure conditions. If one of the external power FETs is destroyed
MC33883
Page 8 of 11
DEVICE DESCRIPTION Figure 5: Limits of C1 Current & Voltage with Large Values dV/dt of Vcc
VCC
Ic1max
tC1min
I[C1+C2]
0A
tc1max
Ic1min
V[LR_OUT]
V[C1]
0V
Vc1min
Over / Under Voltage Shutdown The under voltage protection becomes active at VCC below 5.5 V and the overvoltage protection is activated at VCC above 55 V or at VCC2 above 28 V. If the O/UV protection is activated the outputs are driven low, in order to switch off the FETs. Protection A protection against double battery and load dump spikes up to 55 V is given by VCC = 55 V. A protection against reverse polarity is given by the external power FET with the free wheeling diodes, forming a conducting pass from ground to VCC. An additional protection is not provided within the circuit.
There is a temperature shut down protection per each half bridge. It protects the circuitry against temperature damage by blocking the output drives. Both applications use the internal charge pump to provide the high side floating voltage. This voltage can be provided by an external source also. The following figure shows a typical application. It is worth noting that the supplies VBAT and Vboost may be independant , with different voltage values. In the case of rapidly changing Vboost voltages, the large dv/dt may result in perturbations of the High Side driver such that the driver is forced into an OFF state. The addition of capaitors C1 & C2 reduces the dv/dt of the source line, consequently reducing driver perturbation.
Figure 6: Block Diagram
VBAT VBoost
VCC VCC2 /G_EN CCp
MICRO
CP_OUT LR_OUT FULL BRIDGE PREDRIVER GATE_HS1 SRC_HS1 GATE_LS1 GATE_HS2 SRC_HS2 GATE_LS2 CPout CLRout R1
M1 R2
M3
C1 C2
R3
C1
Load
R4
C2
Load
IN_HS1 IN_LS1 IN_HS2
M2 IN_LS2 GND
M4
MC33883
Page 9 of 11
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Symbol VCC C2 CP_OUT SRC_HS1 GATE_HS1 IN_HS1 IN_LS1 GATE_LS1 GND1 LR_OUT VCC2 GND_A C1 GND2 GATE_LS2 IN_LS2 IN_HS2 GATE_HS2 SRC_HS2 G_EN
Pin Description Supply 1 Charge Pump Capacitor Charge Pump Out Source 1 Output High Side Gate 1 Output High Side Pos. Input High Side 1 Pos. Input High Side 1 Gate 1 Output Low Side Ground Linear Regulator Output Supply 2 Analog Ground Charge Pump Capacitor Ground 2 Gate 2 Output Low Side Pos. Input Low Side 2 Pos. Input High Side 2 Gate 2 Output High Side Source 2 Output High Side Global Enable
MC33883
Page 10 of 11
Package Description
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typical" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or un authorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the parts. Motorola and an Equal Employment Opportunity/Affirmative Action Employer. are registered trademarks of Motorola, Inc. Motorola, Inc. is
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